Real-time High-speed Lossless CompressionCVC Codec (FPGA IP Core)
FPGA-driven High-speed Lossless Data Compression IP Core Series
Designed for natural data such as images and waveforms, CVC Codec is an IP Core that implements our proprietary CVC lossless data compression algorithm with FPGA.
- Run slow and take too long time to complete.
- Processing speed highly depends on the type of input data.
- Not suitable for embedded applications due to requiring a large circuit size.
- Lower compression ratio depending on the data contents.
- Freewares may involve ambiguous licenses.
- General compression means easy decompression.
- Achieves overwhelmingly faster compression than conventional methods.
- Low-latency design ― Compression starts once data is input.
- Stable processing speed and virtually real-time processing.
- Compact circuit size and can be easily implemented into existing systems.
- Higher compression ratio than conventional methods.
- Highly secure due to our proprietary process.
- Includes a free license for a dedicated library for decompression (limited-function version).
CVC Codec: Usage
CVC Codec is constructed in a similar way to FIFO, and passes data via input data (parallel) and control signal (clock, enable, etc) interfaces.
CVC Codec/Encoder outputs compressed data with latency of 2-10 lines after being input digital data such as from sensors.
CVC Codec/Decoder outputs original data with latency of 2-10 lines after being input data compressed by CVC Codec/Encoder.
- Color space: Gray/Bayer/RGB/YUV
- Resolution: 8-16bit
- Pixel Clock: x1/x2/x4/x8
- Various types of XILINX and Intel (ALTERA) devices
For details, please contact us by e-mail.